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QBC Seminar Series – Prashant Nair
May 9, 2023 @ 2:00 pm - 3:00 pm
The Quantum BC Seminar Series is a monthly talk given by faculty in BC on various topics related to quantum computing. The talks happen on the second Tuesday of each month at 2pm.
Please join us for our third seminar with Dr. Prashant Nair on Tuesday, May 9, 2023 at 2pm.
Join on Zoom: https://ubc.zoom.us/j/69443327772?pwd=TGhhTXFIQ3ZiUmNrN0pUa3FObTNydz09
Meeting ID: 694 4332 7772
Passcode: 996727
Optimizing parameters for variational quantum algorithms in the presence of noise is challenging due to the susceptibility of the algorithm to noise. In our approach, we address this challenge by utilizing the parameter transfer technique, which involves first identifying optimal parameters for a smaller instance of the problem and then transferring those parameters to the larger instance. By doing so, we can reduce the impact of noise on the optimization process and improve the accuracy of the optimizer. Our experimental results demonstrate that our technique effectively reduces the circuit size by 28% in terms of qubit counts and 38% in terms of circuit depth, leading to optimal points that are closer to the globally optimal points than the baseline. This approach has potential applications in quantum computing and can enable more accurate solutions for larger instances of problems.
Biography:
Prashant Nair is an Assistant Professor at the University of British Columbia (UBC). His primary interests are Computer Architecture, Quantum Systems, AI/ML Systems, Memory Systems, Reliability, and Security. He leads the “Systems and Architectures (STAR) Lab.” Dr. Nair has 25 publications in top-tier venues such as ISCA, MICRO, HPCA, ASPLOS, DSN, and VLDB. He has received several awards, including the best paper at HPCA 2023, two IEEE MICRO Top-Picks honourable mentions, and the ECE Graduate Research Assistant Excellence Award for his Ph.D. at Georgia Tech. Before joining UBC, he investigated practical data compression for IBM systems at T. J. Watson Research Center in New York. Dr. Nair’s works have had a commercial impact. Specifically, his work on integrating On-Die Error Correcting Code and Host Error Correcting Code (published in ISCA-2016) has been successfully integrated into the HBM3 Memory Protocol by JEDEC consortium. Furthermore, top industry players employ ideas similar to his work (CAL-2014) on probabilistic Row Hammer mitigation in DRAM-based memory systems.